Recently, the development of phase change memory pcm motivates new hybrid memory architectures that consist of pcm and dram. Memristor magnetic spin phase change memory pcm supports new applications no longer require slow, blockbased persistence persisten byte addressable sram l2l3 dram scm flash hdd access latency. From these achievements, we can safely predict that pcm. At present technology nodes, pcm is architected as a flash replacement. A study of application performance with nonvolatile main. Memory technology scaling is in jeopardy as charge storage and sensing mechanisms becomes less reliable for prevalent memory. To make things concrete, we describe a nearterm design for main memory based on a hybrid of. Meza, chang, yoon, mutlu, ranganathan, enabling efficient and scalable hybrid.
Rethinking computer architectures and software systems for. Intel technology journal volume 17, issue 1, 20 using presentday architectural design concepts to drive forward the design of nextgeneration largescale systems is an attractive approach but is inherently misguided. Alternative technologies for memory circuits, including phase change memory pcm, are now being pursued. A study of application performance with nonvolatile main memory. From devices to systems synthesis lectures on computer architecture. As a result, parallel reduction is slow and not scalable. The drams memory cell is based on storing charge on a capacitor. Figure 2 shows three alternative proposals in recent stud. Department of electrical and computer engineering, university of california, santa barbara, ca 93106, usa hp labs, palo alto, ca 94304, usa. New nonvolatile resistive memory elements such as resistive switching memory rram 22, phase change memory pcm 23, conductive bridge memory cbram 24, and ferroelectric memory feram 25 have characteristics that are desirable as electronic synapses spintransfertorque memory. Architecting phase change memory as a scalable dram alternative benjamin leey, engin ipeky, onur mutluz, doug burgery y computer architecture group microsoft research z computer architecture lab carnegie mellon university international symposium on computer architecture. Intel and micron jointly announced a new type of memory today that marries the best attributes of nand flash and dram in a single package. Voltage and frequency scaling in dram howard david, chris fallin, eugene gorbatov. Scalable router memory architecture based on interleaved dram.
Request pdf a novel page replacement algorithm for the hybrid memory architecture involving pcm and dram recently, the development of phase change memory pcm motivates new hybrid memory. Rethinking computer architectures and software systems for phasechange memory 33. In one embodiment, a pcm architecture includes a pcm array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as dram.
A study of application performance with nonvolatile main memory yiying zhang university of california, san diego. Phase change memory devices are currently wellpositioned to be used in the exploration of neuromorphic and memcomputing applications owing to the multilevel storage capability, proven large. Intel, micron reveal xpoint, a new memory architecture that. Dram bank unavailable while refreshed long pause times. Introduction field programmable gate arrays fpgas have become a viable alternative to custom integrated circuits ics by. Although they are produced in many sizes and sold in a variety of packages, their overall operation is essentially the same. In contrast, phase change memory pcm relies on programmable resistances, as. Device and system level design considerations for analognon. A scalable io architecture for wide io dram qawi harvard and r. Dram an advantage of dram over other types of memory is its ability to be implemented with fewer circuits per memory cell on the ic integrated circuit. Permission to make digital or hard copies of all or part of this work for. Architectures, interfaces, and systems to improve your computer architecture skills and better understand memory this course is adapted to your level as well as all memory pdf courses to better enrich your knowledge all you need to do is download the training document, open it and start learning memory for free. Leuven esat micas laboratory kasteelpark arenberg 10, leuven, belgium anselme.
In contrast, phase change memory pcm storage relies on scalable current and thermal mechanisms. Such performance might be achieved by advances that make nvram cells as fast as dram cells or through the use of nonvolatile caches and enough re. Scalable high performance main memory system using. In this paper, we propose new architectural support to speedup parallel reductions in scalable shared memory multiprocessors. An operating system level data migration scheme in hybrid. The memory forum 2014 1 co architecting controllers and dram. A high bandwidth and scalable memory system kanit therdsteerasukdi1, gyungsu byun2, jeremy ir3. Dram form factors no passive power consumption persistent types. Intel, micron reveal xpoint, a new memory architecture.
Operating system implications of fast, cheap, nonvolatile. Dram, cache, mram, and phase change memory can be combined and. Coen4730 computer architecture lecture 5 main memory cristinel ababei dept. Proposed hybrid memory using dram and pcm to attain better performance.
A typical dram cell is built with one capacitor and one or three fets fieldeffect transistor. Jacob baker department of electrical and computer engineering boise state university boise, id, u. Design and performance analysis of a drambased statistics. Hybrid cache architecture replacing sram cache with future memory technology suji lee, jongpil jung, and chongmin kyung. Modeling power consumption of nand flash memories using. Understanding dram operation 1296 page 1 overview dynamic random access memory dram devices are used in a wide range of electronics applications. Lecture 2 spring 2003 bruce jacob david wang university of maryland dram circuit and architecture basics overview terminology access protocol architecture storage element switching element bit line word line capacitor. Meza, chang, yoon, mutlu, ranganathan, enabling efficient and scalable hybrid memories, ieee. Phasechange memory devices are currently wellpositioned to be used in the exploration of neuromorphic and memcomputing applications owing. Kubiatowicz, patterson, mutlu, elsevier 2 outline main memory organization dram basics quest for dram performance memory. Dram ddrxlpddrx architecture training let mindshare bring dram ddrxlpddrx architecture to life for you ever since intel introduced dram memory, it has evolved in size, density, speed and architecture. Some devices show gradual resistance change only in one direction set or reset.
A novel dram architecture as a low leakage alternative for. Phase change memory pcm is an emerging memory tech. The electrical and thermal proper ties of phase change materials are surveyed with a focus on the scalability of the materials and. Architecting phase change memory as a scalable dram alternative. Scalable manycore memory systems lecture 3, topic 1. Lee, ipek, mutlu, burger, architecting phase change memory as a scalable dram alternative, isca 2009, cacm 2010, top picks 2010. Coen4730 computer architecture lecture 5 main memory.
A novel page replacement algorithm for the hybrid memory. Phase change memory pcm supports new applications no longer require slow. Pdf proposed hybrid memory using dram and pcm to attain. Shut down dram devices when no memory requests active. This work was supported in part by nsf 0702617, 0916887, 0903432, and src grants. Modeling power consumption of nand flash memories using flashpower vidyabhushan mohan, trevor bunker, laura grupp, sudhanva gurumurthi senior member, ieee, mircea r. Among these, phase change memory pcm is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. Hybrid main memories composed of dram as a cache to scalable nonvolatile memories such as phase change memory pcm can. Phase change memory pcm is emerging as a leading contender, and the authors discuss the material, device, and. A novel processinginmemory architecture for neural network computation in rerambased main memory ping chi. Memory technology scaling is in jeopardy as charge storage and sensing mechanisms becomes less reliable for prevalent memory technologies, such as flash and dram. Oct 04, 2012 a phase change memory pcm architecture and a method for writing into a pcm architecture are described.
For dram technology, a doublegate array having vertical channel structure dgvc with 4f2 cell size is proposed, which can be fabricated on a bulk silicon wafer using the conventional memory process flow for standalone dram application. In this paper, we propose new architectural support to speedup parallel reductions in scalable sharedmemory multiprocessors. Projected phasechange memory devices nature communications. Two transfers per clock on rising and falling edge intel claims fbdimm is the next big thing stands for fullybuffered dualinline ram same basic technology as ddr, but utilizes a serial daisy. Operating system implications of fast, cheap, nonvolatile memory.
Architecting phase change memory as a scalable dram alternative presented by skanda koppula december 2018 benjamin c. Phase change memory pcm is arguably the most advanced nonvolatile memory candidate that could serve many of these applications. Pcm storage relies on scalable current and thermal mecha nisms. An energyefficient and scalable edrambased register file. To mitigate the impact of periodic refresh, we propose two novel refresh solutions using bank. Phase change memory architecture and the quest for. A range of consumer electronics products, such as cell. Evaluating sttram as an energyefficient main memory.
B lower static power with resistive memory i pcm on memory bus b exploit low latencies, byteaddressability b explore buffer design, wear reductionleveling i pcm as dram alternative b 1. Hybrid main memories composed of dram as a cache to scalable nonvolatile memories such as. Dram microarchitecture memory controller memory buses banks. Static random access memory sram is used as cache memory in most microprocessors since sram has very high speed. Slides adapted from presentations of sudeep pasricha and others. Drams are designed for the sole purpose of storing data. Scalable high performance main memory system using phase. This is the most advanced alternative, as it requires nvram to be as fast as dram so that the nonvolatility of memory does not come at a performance cost. This is the most advanced alternative, as it requires nvram to be as fast as dram so that the nonvolatility of memory does not come at a.
A phase change memory as a secure main memory halinria. Abstractphase change memory pcm technology appears as more scalable than dram technology. Phasechange memory pcm is arguably the most advanced nonvolatile memory candidate that could serve many of these applications. To exploit pcms scalability as a dram alternative, pcm must be architected to address relatively long. The shrinking dimensions of devices place strong limitations on the continued use of dynamic random access memory dram architectures. Same basic technology as ddr, but utilizes a serial daisy. The memory forum 2014 1 co architecting controllers and dram to enhance dram process scaling uksong kang, haksoo yu, churoo park, hongzhong zheng, john halbert, kuljit bains, seongjin jang, and joo sun choi. Could this be the longsought solution to the industrys. Scalable router memory architecture based on interleaved. Evaluating phase change memory for enterprise storage. Phase change memory pcm devices offer more density relative to dram, and can help increase main memory capacity of future systems while.
Architecting phase change memory as a scalable dram alternative, isca 2009, cacm 2010, top picks 2010. Architecting phase change memory as a scalable dram alternative conference paper in acm sigarch computer architecture news 373. Architectural support for parallel reductions in scalable. Abstracta 4 gb dram architecture utilizing a scalable number of data pins is proposed. A phase change memory pcm architecture and a method for writing a pcm architecture are described. Dram, cache, mram, and phase change memory can be combined and when supported with the right software, can provide phenomenal growth opportunities. We present an analysis of storage application performance with nonvolatile main memory nvmm using a hardware nvmm emulator. Architecting phase change memory as a scalable dram alternative benjamin c. Design and performance analysis of a drambased statistics counter array architecture haiquan chuck zhaoy hao wangx bill linx jun jim xuy ycollege of computing georgia institute of technology xdepartment of electrical and computer engineering university of california, san diego. The memory forum 2014 1 coarchitecting controllers and dram to enhance dram process scaling uksong kang, haksoo yu, churoo park, hongzhong zheng, john halbert, kuljit bains, seongjin jang, and joo sun choi.
A novel processinginmemory architecture for neural. Two transfers per clock on rising and falling edge intel claims fbdimm is the next big thing. The memory forum 2014 1 co architecting controllers and. An important issue in such hybrid memory architectures is how to manage the pages resisting in heterogeneous memories. Lecture 2 spring 2003 bruce jacob david wang university of maryland row row address. Stan senior member, ieee, and steven swanson abstract flash is the most popular solidstate memory technology used today. Table i summarizes the characteristics of different nvm technologies and compares them to traditional memory and storage. Storage systems based on phase change memory pcm devices are beginning. A novel dram architecture as a low leakage alternative for sram caches in a 3d interconnect context. Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as dynamic random access memory dram. Jul 28, 2015 intel and micron jointly announced a new type of memory today that marries the best attributes of nand flash and dram in a single package.
In contrast, phase change memory pcm relies on programmable resistances, as well as scalable current and thermal mechanisms. Hybrid cache architecture replacing sram cache with future. Phase change memory stanford nanoheat stanford university. Architecting phase change memory as a scalable dram alternative benjamin leey, engin ipeky, onur mutluz, doug burgery y computer architecture group microsoft research z computer architecture lab. Architecting phase change memory as a scalable dram. But, even lowmemorybandwidth workloads keep memory. Rethinking database algorithms for phase change memory cidr.
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